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| january 2000 1/22 rev. 2.5 ST92195B 32-64k rom hcmos mcu with on-screen-display and teletext data slicer data briefing n register file based 8/16 bit core architecture with run, wfi, slow and halt modes n 0 c to +70 c operating temperature range n up to 24 mhz. operation @ 5v 10% n min. instruction cycle time: 165ns at 24 mhz. n 32, 48, 56 or 64 kbytes rom n 256 bytes ram of register file (accumulators or index registers) n 256 bytes of on-chip static ram n 2, 6 or 8 kbytes of tdsram (teletext and display storage ram) n 28 fully programmable i/o pins n serial peripheral interface n flexible clock controller for osd, data slicer and core clocks running from a single low frequency external crystal. n enhanced display controller with 26 rows of 40/80 characters serial and parallel attributes 10x10 dot matrix, 512 rom characters, defin- able by user 4/3 and 16/9 supported in 50/60hz and 100/ 120 hz mode rounding, fringe, double width, double height, scrolling, cursor, full background color, half- intensity color, translucency and half-tone modes n teletext unit, including data slicer, acquisition unit and up to 8 kbytes ram for data storage n vps and wide screen signalling slicer (on some devices) n integrated sync extractor and sync controller n 14-bit voltage synthesis for tuning reference voltage n up to 6 external interrupts plus one non- maskable interrupt n 8 x 8-bit programmable pwm outputs with 5v open-drain or push-pull capability n 16-bit watchdog timer with 8-bit prescaler n one 16-bit standard timer with 8-bit prescaler n 4-channel a/d converter; 5-bit guaranteed n rich instruction set and 14 addressing modes n versatile development tools, including assembler, linker, c-compiler, archiver, source level debugger and hardware emulators with real-time operating system available from third parties n pin-compatible eprom and otp devices available device summary device program memory tds ram vps/ wss package ST92195B1 32k rom 2k yes psdip56/ tqfp64 ST92195B2 32k rom 6k no ST92195B3 32k rom 6k yes ST92195B4 48k rom 6k yes ST92195B5 48k rom 8k yes ST92195B6 56k rom 8k yes ST92195B7 64k rom 8k yes st92t195b7 64k otp 8k yes st92e195b7 64k eprom 8k yes csdip56 /cqfp64 tqfp64 psdip56 see end of document for ordering information 1
2/22 ST92195B - general description 1 general description 1.1 introduction the ST92195B microcontroller is developed and manufactured by stmicroelectronics using a pro- prietary n-well hcmos process. its performance derives from the use of a flexible 256-register pro- gramming model for ultra-fast context switching and real-time event response. the intelligent on- chip peripherals offload the st9 core from i/o and data management processing tasks allowing criti- cal application tasks to get the maximum use of core resources. the ST92195B mcu supports low power consumption and low voltage operation for power-efficient and low-cost embedded systems. 1.1.1 st9+ core the advanced core consists of the central processing unit (cpu), the register file and the interrupt controller. the general-purpose registers can be used as ac- cumulators, index registers, or address pointers. adjacent register pairs make up 16-bit registers for addressing or 16-bit processing. although the st9 has an 8-bit alu, the chip handles 16-bit opera- tions, including arithmetic, loads/stores, and mem- ory/register and memory/memory exchanges. two basic addressable spaces are available: the memory space and the register file, which in- cludes the control and status registers of the on- chip peripherals. 1.1.2 power saving modes to optimize performance versus power consump- tion, a range of operating modes can be dynami- cally selected. run mode. this is the full speed execution mode with cpu and peripherals running at the maximum clock speed delivered by the phase locked loop (pll) of the clock control unit (ccu). wait for interrupt mode. the wait for interrupt (wfi) instruction suspends program execution un- til an interrupt request is acknowledged. during wfi, the cpu clock is halted while the peripheral and interrupt controller keep running at a frequen- cy programmable via the ccu. in this mode, the power consumption of the device can be reduced by more than 95% (low power wfi). halt mode. when executing the halt instruction, and if the watchdog is not enabled, the cpu and its peripherals stop operating and the status of the machine remains frozen (the clock is also stopped). a reset is necessary to exit from halt mode. 1.1.3 i/o ports up to 28 i/o lines are dedicated to digital input/ output. these lines are grouped into up to five i/o ports and can be configured on a bit basis under software control to provide timing, status signals, timer and output, analog inputs, external interrupts and serial or parallel i/o. 1.1.4 tv peripherals a set of on-chip peripherals form a complete sys- tem for tv set and vcr applications: voltage synthesis vps/wss slicer teletext slicer teletext display ram osd 1.1.5 on screen display the human interface is provided by the on screen display module, this can produce up to 26 lines of up to 80 characters from a rom defined 512 char- acter set. the character resolution is 10x10 dot. four character sizes are supported. serial at- tributes allow the user to select foreground and background colors, character size and fringe back- ground. parallel attributes can be used to select additional foreground and background colors and underline on a character by character basis. 1.1.6 teletext and display storage ram the internal teletext and display storage ram can be used to store teletext pages as well as dis- play parameters. 3/22 ST92195B - general description introduction (cont'd) 1.1.7 teletext, vps and wss data slicers the three on-board data slicers using a single ex- ternal crystal are used to extract the teletext, vps and wss information from the video signal. hard- ware hamming decoding is provided. 1.1.8 voltage synthesis tuning control 14-bit voltage synthesis using the pwm (pulse width modulation)/brm (bit rate modulation) technique can be used to generate tuning voltages for tv set applications. the tuning voltage is out- put on one of two separate output pins. 1.1.9 pwm output control of tv settings can be made with up to eight 8-bit pwm outputs, with a maximum frequen- cy of 23,437hz at 8-bit resolution (intclk = 12 mhz). low resolutions with higher frequency oper- ation can be programmed. 1.1.10 serial peripheral interface (spi) the spi bus is used to communicate with external devices via the spi, or i c bus communication standards. the spi uses a single data line for data input and output. a second line is used for a syn- chronous clock signal. 1.1.11 standard timer (stim) the ST92195B has one standard timer (stim0) that includes a programmable 16-bit down counter and an associated 8-bit prescaler with single and continuous counting modes. 1.1.12 analog/digital converter (adc) in addition there is a 4-channel analog to digital converter with integral sample and hold, fast 5.75 m s conversion time and 6-bit guaranteed reso- lution. 4/22 ST92195B - general description introduction (cont'd) figure 1. ST92195B block diagram memory bus i/o port 0 register bus voltage synthesis pwm d/a con- verter spi i/o port 4 i/o port 5 up to 64 kbytes rom data slicer & acqui- sitio n unit sync. extrac- tion up to 8 kbytes tdsram tri 256 bytes ram standard timer timing and clock ctrl 16-bit timer/ watchdog vps/wss data slicer i/o port 2 adc cvbs1 i/o port 3 sync control vsync hsync/csync on screen display freq. multip. pxfm nmi int[7:4] int2 256 bytes register file st9+ core 8/16-bit cpu interrupt management rccu oscin oscout reset reseto p0[7:0] wscr wscf cvbs2 r/g/b/fb pwm[7:0] sdo/sdi sck int0 stout mmu mcfm txcf tslu ain[4:1] vso[2:1] extrg p2[5:0] p4[7:0] p5[1:0] p3[7:4] cso ht all alternate functions (italic characters) are mapped on ports 0, 2, 3, 4 and 5 2 8 4 6 8 5/22 ST92195B - general description 1.2 pin description figure 2. 64-pin package pin-out n.c. = not connected gnd ain4/p0.2 p0.1 p0.0 cso/reset0/p3.7 p3.6 p3.5 p3.4 b g r fb sdo/sdi/p5.1 int2/sck/p5.0 v dd jtdo v dd p0.3 p0.4 p0.5 p0.6 p0.7 reset p2.0/int7 p2.1/int5/ain1 p2.2/int0/ain2 p2.3/int6/vs01 p2.4/nmi p2.5/ain3/int4/vs02 oscin oscout v dd v ss p4.7/pwm7/extrg/stout p4.6/pwm6 p4.5/pwm5 p4.4/pwm4 p4.3/pwm3/tslu/ht p4.2/pwm2 p4.1/pwm1 p4.0/pwm0 vsync hsync/csync avdd1 pxfm jtrst0 gnd n.c. n.c. n.c. wscf v pp /wscr avdd3 test0 mcfm jtck txcf cvbso avdd2 jtms cvbs2 cvbs1 agnd n.c. 1 64 16 32 48 16 6/22 ST92195B - general description pin description (cont'd) reset reset (input, active low). the st9+ is ini- tialised by the reset signal. with the deactivation of reset, program execution begins from the program memory location pointed to by the vector contained in program memory locations 00h and 01h. r/g/b red/green/blue . video color analog dac outputs. fb fast blanking . video analog dac output. v dd main power supply voltage (5v 10%, digital) wscf, wscr analog pins for the vps/wss slic- er . these pins must be tied to ground or not con- nected. v pp : on eprom/otp devices, the wscr pin is replaced by v pp which is the programming voltage pin. v pp should be tied to gnd in user mode. mcfm analog pin for the display pixel frequency multiplier. oscin, oscout oscillator (input and output). these pins connect a parallel-resonant crystal (24mhz maximum), or an external source to the on-chip clock oscillator and buffer. oscin is the input of the oscillator inverter and internal clock generator; oscout is the output of the oscillator inverter. vsync vertical sync . vertical video synchronisa- tion input to osd. positive or negative polarity. hsync/csync horizontal/composite sync . hori- zontal or composite video synchronisation input to osd. positive or negative polarity. pxfm analog pin for the display pixel frequency multiplier avdd3 analog v dd of pll. this pin must be tied to v dd externally. gnd digital circuit ground. agnd analog circuit ground (must be tied exter- nally to digital gnd). cvbs1 composite video input signal for the tele- text slicer and sync extraction. cvbs2 composite video input signal for the vps/ wss slicer. pin ac coupled. avdd1, avdd2 analog power supplies (must be tied externally to avdd3). txcf analog pin for the teletext slicer line pll. cvbso, jtdo, jtck test pins: leave floating. test0 test pins: must be tied to avdd2. jtrst0 test pin: must be tied to gnd. figure 3. 56-pin package pin-out int7/p2.0 reset p0.7 p0.6 p0.5 p0.4 p0.3 ain4/p0.2 p0.1 p0.0 cso/re set0/p3.7 p3.6 p3.5 p3.4 b g r fb sdi/sdo/ p5.1 sck/int2/p5. 0 v dd jtdo wscf v pp /wscr avdd3 test 0 mcfm jtck p2.1/int5/ain1 p2.2/int0/ain2 p2.3/int6/vs01 p2.4/nmi p2.5/ain3/int4/vs02 oscin oscout p4.7/pwm7/ex trg/st out p4.6/pwm6 p4.5/pwm5 p4.4/pwm4 p4.3/pwm3/tslu/ht p4.2/pwm2 p4.1/pwm1 p4.0/pwm0 vsync hsync/csync avdd1 pxfm jtrsto gnd agnd cvbs1 cvbs2 jtms avdd2 cvbso txcf 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 7/22 ST92195B - general description pin description (cont'd) figure 4. ST92195B required external components (56-pin package) +5v +5v p20 p24 p05 p50 p46 p37 p47 p04 p45 p03 p01 p44 p07 p36 p51 p21 p02 p00 p43 p41 p22 p35 p34 p25 p42 p40 p23 p06 c16 2.2nf r4 15k c13 4.7nf c10 4.7nf c3 82pf c1 82pf r2 5.6k r3 5.6k c14 82pf c11 22pf c2 1 m f s1 rst d1 1n4148 c12 470nf c8 22pf c7 10 m f c9 100 nf c5 100nf c15 100nf c6 100nf c4 10 m f l1 10uh r1 10k l2 10uh y1 4mhz u1 sdip56 ST92195B 1 56 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 p2.0/int7 p2.1/int5/ain1 resetn p0.7 p0.6 p0.5 p0.4 p0.3 p0.2/ain4 p0.1 p0.0 p3.7/reset0/cso p3.6 p3.5 p3.4 b g r fb p5.1/sdi/sdo p5.0/sck/int2 vdd jtdo wscf wscr avdd3 test0 mcfm jtck p2.2/int0/ain2 p2.3/int6 /vs01 p2.4/nmi p2.5/ain3/int4/vs02 oscin oscout p4.7/pwm7/extrg/stout p4.6/pwm6 p4.5/pwm5 p4.4/pwm4 p4.3/pwm3 /tslu/ht p4.2/pwm2 p4.1/pwm1 p4.0/pwm0 vsync hsy nc/csync avdd1 pxfm jtrst0 gnd agnd cvbs1 cvbs2 jtms avdd2 cvbso txcf cvbs fb vsync r b h sync g 8/22 ST92195B - general description pin description (cont'd) figure 5. ST92195B required external components (64-pin package) +5v +5v p20 p25 p36 p05 p46 p03 p35 p40 p06 p45 p34 p42 p07 p44 p5.1 p37 p43 p21 p47 p24 p01 p41 p22 p00 p04 p02 p23 p5.0 r2 5.6k y1 4mhz r3 5.6k r1 10k d1 1n4148 l2 10uh l1 10uh c12 100nf c2 82pf s1 rst c13 10uf c4 82pf c15 4.7nf c1 1 m f c5 10uf c7 100nf c14 22pf c9 22pf c3 100nf c6 100nf c8 100nf c10 4.7nf c11 100nf u1 qfp64 ST92195B 1 56 2 3 4 5 6 7 8 9 10 11 12 13 14 15 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 23 18 19 20 21 22 24 25 26 27 28 17 16 57 58 59 60 61 62 63 64 vss p2.1/int5/ain1 p0.2/ain4 p0.1 p0.0 p3.7/reset0/cso p3.6 p3.5 p3.4 b g r fb p5.1/sdi/sdo p5.0/sck/int2 vdd p2.2/int0/ain2 p2.3/int6/vs01 p2.4/nmi p2.5/ain3/int4/vs02 oscin oscout vdd gnd extrg/slout/p4.7/pwm7 p4.6/pwm6 p4.5/pwm5 p4.4/pwm4 ht/tslu/p4.3/pwm3 p4.2/pwm2 p4.1/pwm1 p4.0/pwm0 vsync csync/hsync avdd1 pxfm jtrst0 gnd nc nc agnd cvbs1 cvbs2 mcfm nc wscf wscr avdd3 test0 jtck txcf cvbso avdd2 jtms nc jtdo int7/p2.0 resetn p0.7 p0.6 p0.5 p0.4 p0.3 vdd g b r fb hsync vsync 9/22 ST92195B - general description pin description (cont'd) p0[7:0], p2[5:0], p3[7:4], p4[7:0], p5[1:0] i/o port lines (input/output, ttl or cmos com- patible). 28 lines grouped into i/o ports, bit programmable as general purpose i/o or as alternate functions (see i/o section). important : note that open-drain outputs are for logic levels only and are not true open drain. 1.2.1 i/o port alternate functions. each pin of the i/o ports of the ST92195B may as- sume software programmable alternate functions (see table 1). table 1. ST92195B i/o port alternate function summary port name general purpose i/o pin no. alternate functions tqfp64 sdip56 p0.0 all ports useable for general pur- pose i/o (input, output or bidi- rectional) 4 10 i/o p0.1 3 9 i/o p0.2 2 8 ain4 i a/d analog data input 4 p0.3 63 7 i/o p0.4 62 6 i/o p0.5 61 5 i/o p0.6 60 4 i/o p0.7 59 3 i/o p2.0 57 1 int7 i external interrupt 7 p2.1 56 56 ain1 i a/d analog data input 1 int5 i external interrupt 5 p2.2 55 55 int0 i external interrupt 0 ain2 i a/d analog data input 2 p2.3 54 54 int6 i external interrupt 6 vso1 o voltage synthesis output 1 p2.4 53 53 nmi i non maskable interrupt input p2.5 52 52 ain3 i a/d analog data input 3 int4 i external interrupt 4 vso2 o voltage synthesis output 2 p3.4 8 14 i/o p3.5 7 13 i/o p3.6 6 12 i/o p3.7 5 11 reset0 o internal reset output cso o composite sync output p4.0 40 42 pwm0 o pwm output 0 p4.1 41 43 pwm1 o pwm output 1 p4.2 42 44 pwm2 o pwm output 2 p4.3 43 45 pwm3 o pwm output 3 tslu o translucency digital output ht o half-tone output p4.4 44 46 pwm4 o pwm output 4 10/22 ST92195B - general description 1.2.2 i/o port styles legend: af= alternate function, bid = bidirectional, od = open drain pp = push-pull, ttl = ttl standard input levels how to read this table to configure the i/o ports, use the information in this table and the port bit configuration table in the i/o ports chapter of the datasheet. port style = the hardware characteristics fixed for each port line. inputs: if port style = standard i/o, either ttl or cmos input level can be selected by software. if port style = schmitt trigger, selecting cmos or ttl input by software has no effect, the input will always be schmitt trigger. weak pull-up = this column indicates if a weak pull-up is present or not. if wpu = yes, then the wpu can be enabled/dis- able by software if wpu = no, then enabling the wpu by software has no effect alternate functions (af) = more than one af cannot be assigned to an external pin at the same time: an alternate function can be selected as follows. af inputs: af is selected implicitly by enabling the corre- sponding peripheral. exception to this are adc analog inputs which must be explicitly selected as af by software. p4.5 all ports useable for general pur- pose i/o (input, output or bidi- rectional) 45 47 pwm5 o pwm output 5 p4.6 46 48 pwm6 o pwm output 6 p4.7 47 49 extrg i a/d converter external trigger input pwm7 o pwm output 7 stout o standard timer output p5.0 14 20 int2 i external interrupt 2 sck o spi serial clock p5.1 13 19 sdo o spi serial data out sdi i spi serial data in port name general purpose i/o pin no. alternate functions tqfp64 sdip56 pins weak pull-up port style reset values p0[7:0] no standard i/o bid / od / ttl p2[5,4,3,2] no standard i/o bid / od / ttl p2[1,0] no schmitt trigger bid / od / ttl p3.7 yes standard i/o af / pp / ttl p3[6,5,4] no standard i/o bid / od / ttl p4[7:0] no standard i/o bid / od / ttl p5[1:0] no standard i/o bid / od / ttl 11/22 ST92195B - general description pin description (cont'd) af outputs or bidirectional lines: in the case of outputs or i/os, af is selected explicitly by software. example 1: adc trigger digital input af: extrg, port: p4.7, port style: standard i/o. write the port configuration bits (for ttl level): p4c2.7=1 p4c1.7=0 p4c0.7=1 enable the adc trigger by software as described in the adc chapter. example 2: pwm 0 output af: pwm0, port: p4.0 write the port configuration bits (for output push- pull): p4c2.0=0 p4c1.0=1 p4c0.0=1 example 3: adc analog input af: ain1, port : p2.1, port style: does not apply to analog inputs write the port configuration bits: p2c2.1=1 p2c1.1=1 p2c0.1=1 12/22 ST92195B - general description 1.3 memory map internal rom the rom memory is mapped in a single continu- ous area starting at address 0000h in mmu seg- ment 00h. internal ram, 256 bytes the internal ram is mapped in mmu segment 20h; from address ff00h to ffffh. internal tdsram the internal tdsram is mapped starting at ad- dress 8000h in mmu segment 22h. it is a fully stat- ic memory. figure 6. ST92195B memory map device size start address end address ST92195B1/b2/b3 32k 0000h 7fffh ST92195B4/b5 48k 0000h bfffh ST92195B6 56k 0000h dfffh ST92195B7 64k 0000h ffffh device size start address end address ST92195B1 2k 8000h 87ffh ST92195B2/b3/b4 6k 8000h 97ffh ST92195B5/b6/b7 8k 8000h 9fffh segment 0 64 kbytes 00ffffh 00c000h 00bfffh 008000h 007fffh 004000h 000000h 003fffh page 0 - 16 kbytes page 1 - 16 kbytes page 2 - 16 kbytes page 3 - 16 kbytes segment 20h 64 kbytes 200000h 21ffffh 20c000h 20bfffh 208000h 207fffh 204000h 203fffh page 80 - 16 kbytes page 81 - 16 kbytes page 82 - 16 kbytes page 83 - 16 kbytes 20ff 00h 20ffffh ram 256 bytes internal reserved segment 21h 64 kbytes 20ffffh 220000h 22ffffh 210000h segment 22h 64 kbytes 228000h 229fffh max. 8 kbytes tdsram internal rom page 88 - 16 kbytes page 89 - 16 kbytes page 90 - 16 kbytes page 91 - 16 kbytes 22c000h 22bfffh 228000h 227fffh 224000h 223fffh reserved reserved reserved reserved reserved reserved max. 64 kbytes 13/22 ST92195B - electrical characteristics 2 electrical characteristics absolute maximum ratings note : stress above those listed as aabsolute maximum ratingso may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. recommended operating conditions symbol parameter value unit v dd supply voltage v ss - 0.3 to v ss + 7.0 v v ssa analog ground v ss - 0.3 to v ss + 0.3 v v dda analog supply voltage v dd -0.3 to v dd +0.3 v v i input voltage v ss - 0.3 to v dd +0.3 v v ai analog input voltage (a/d converter) v ss - 0.3 to v dd +0.3 v ssa - 0.3 to v dda +0.3 v v o output voltage v ss - 0.3 to v dd + 0.3 v t stg storage temperature - 55 to + 150 c i inj pin injected current maximum accumulated pin injected current in device -5to+5 -50to+50 ma ma symbol parameter value unit min. max. t a operating temperature 0 70 c v dd supply voltage 4.5 5.5 v v dda analog supply voltage (pll) 4.5 5.5 v f osce external oscillator frequency 3.3 8.7 mhz f osci internal clock frequency (intclk) 24 mhz 14/22 ST92195B - electrical characteristics dc electrical characteristics ( v dd = 5v +/-10%; t a = 0 to 70 c; unless otherwise specified) symbol parameter test conditions value unit min. max. v ihck clock in high level external clock 0.7 v dd v v ilck clock in low level external clock 0.3 v dd v v ih input high level ttl 2.0 v v il input low level ttl 0.8 v v ih input high level cmos 0.8 v dd v v il input low level cmos 0.2 v dd v v ihrs reset in high level 0.7 v dd v v ilrs reset in low level 0.3 v dd v v hyrs reset in hysteresis 0.3 v v ihy p2.(1:0) input hysteresis 0.9 v v ihvh hsync/vsync input high level 0.7 v dd v v ilvh hsync/vsync input low level 0.3 v dd v v hyhv hsync/vsync input hysteresis 0.5 v v oh output high level push-pull ild=-0.8ma v dd -0.8 v v ol output low level push-pull ld=+1.6ma 0.4 v i wpu weak pull-up current bidir. state v ol =3v v ol =7v 50 350 m a i lkio i/o pin input leakage current 0 16/22 ST92195B - electrical characteristics ac electrical characteristics (cont'd) spi timing table ( v dd = 5v +/-10%; t a = 0 to 70 c; cload= 50pf) (1) tpc is the oscin clock period; tpmc is the amain clock frequencyo period. skew corrector timing table ( v dd = 5v +/-10%, t a = 0 to 70 c, unless otherwise specified) (*) the osd jitter is measured from leading edge to leading edge of a single character row on consecutive tv lines. the value is an envelope of 100 fields symbol parameter conditi on value unit min max t sdi input data set-up time tbd ns t hdi input data hold time (1) oscin/2 as internal clock 1intclk +100ns ns t dov sck to output data valid tbd ns t hdo output data hold time tbd ns t wskl sck low pulse width tbd ns t wskh sck high pulse width tbd ns symbol parameter conditions max value unit t jskw jitter on rgb output 36 mhz skew corrector clock frequency 5* ns 17/22 ST92195B - electrical characteristics ac electrical characteristics (cont'd) osd dac characteristics (rom devices only) ( v dd = 5v +/-10%, t a = 0 to 70 c, unless otherwise specified). osd dac characteristics (eprom and otp devices only) ( v dd = 5v +/-10%, t a = 0 to 70 c, unless otherwise specified). symbol parameter conditio ns value unit min typical max output impedance: fb,r,g,b 300 500 700 ohm output voltage: fb,r,g,b cload= 20pf rl = 100k code= 111 1.000 1.250 v code= 011 0.450 0.500 v code= 000 0.025 0.080 v fb= 1 2.4 2.7 3.4 v fb= 0 0 0.025 0.080 v global voltage accuracy +/-5 % symbol parameter conditions value unit min typical max output impedance: fb,r,g,b 300 500 700 ohm output voltage: fb,r,g,b cload= 20pf rl = 100k code= 111 1.100 1.400 v code= 011 0.600 0.800 v code= 000 0.200 0.350 v fb= 1 v dd -0.8 v fb= 0 0.400 v global voltage accuracy +/-5 % 18/22 ST92195B - electrical characteristics ac electrical characteristics (cont'd) a/d converter, external trigger timing table ( v dd = 5v +/-10%; t a = 0 to 70 c; unless otherwise specified a/d converter. analog parameters table ( v dd = 5v +/-10%; t a = 0 to 70 c; unless otherwise specified)) notes: (*) the values are expected at 25 celsius degrees with v dd =5v (**) 'lsbs' , as used here, as a value of v dd /256 (1) @ 24 mhz external clock (2) including sample time (3) it must be considered as the on-chip series resistance before the sampling capacitor (4) dnl error= max {[v(i) -v(i-1)] / lsb-1} inl error= max {[v(i) -v(0)] / lsb-i} absolute accuracy= overall max conversion error symbol parameter oscin divide by 2;min/max oscin divide by 1; min/max value unit min max t low pulse width 1.5 intclk ns t high pulse distance ns t ext period/fast mode 78+1 intclk m s t str start conversion delay 0.5 1.5 intclk core clock issued by timing controller t low pulse width ns t high pulse distance ns t ext period/fast mode m s t str start conversion delay ns parameter value unit note typ (*) min max (**) analog input range v ss v dd v conversion time fast/slow 78/138 intclk (1,2) sample time fast/slow 51.5/87.5 intclk (1) power-up time 60 m s resolution 8 bits differential non linearity 1.5 2.5 lsbs (4) integral non linearity 2 3 lsbs (4) absolute accuracy 2 3 lsbs (4) input resistance 1.5 kohm (3) hold capacitance 1.92 pf 19/22 ST92195B - general information 3 general information 3.1 package mechanical data figure 7. 56-pin shrink plastic dual in line package, 600-mil width figure 8. 64-pin thin quad flat package dim. mm inches min typ max min typ max a 6.35 0.250 a1 0.38 0.015 a2 3.18 4.95 0.125 0.195 b 0.41 0.016 b2 0.89 0.035 c 0.20 0.38 0.008 0.015 d 50.29 53.21 1.980 2.095 e 15.01 0.591 e1 12.32 14.73 0.485 0.580 e 1.78 0.070 ea 15.24 0.600 eb 17.78 0.700 l 2.92 5.08 0.115 0.200 number of pins n56 pdip56s dim mm inches min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.015 0.018 c 0.09 0.20 0.004 0.008 d 16.00 0.630 d1 14.00 0.551 d3 12.00 0.472 e 16.00 0.630 e1 14.00 0.551 e3 12.00 0.472 e 0.80 0.031 k 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n 64 nd 16 ne 16 l1 l k 20/22 ST92195B - general information package mechanical data (cont'd) figure 9. 56-pin shrink ceramic dual in line package, 600-mil width figure 10. 64-pin ceramic quad flat package dim. mm inches min typ max min typ max a 4.17 0.164 a1 0.76 0.030 b 0.38 0.46 0.56 0.015 0.018 0.022 b1 0.76 0.89 1.02 0.030 0.035 0.040 c 0.23 0.25 0.38 0.009 0.010 0.015 d 50.04 50.80 51.56 1.970 2.000 2.030 d1 48.01 1.890 e1 14.48 14.99 15.49 0.570 0.590 0.610 e 1.78 0.070 g 14.12 14.38 14.63 0.556 0.566 0.576 g1 18.69 18.95 19.20 0.736 0.746 0.756 g2 1.14 0.045 g3 11.05 11.30 11.56 0.435 0.445 0.455 g4 15.11 15.37 15.62 0.595 0.605 0.615 l 2.92 5.08 0.115 0.200 s 1.40 0.055 number of pins n56 cdip56sw dim mm inches min typ max min typ max a 3.27 0.129 a1 0.50 0.020 b 0.30 0.35 0.45 0.012 0.014 0.018 c 0.13 0.15 0.23 0.005 0.006 0.009 d 16.65 17.20 17.75 0.656 0.677 0.699 d1 13.57 13.97 14.37 0.534 0.550 0.566 d3 12.00 0.472 e 0.80 0.031 g 12.70 0.500 g2 0.96 0.038 l 0.35 0.80 0.014 0.031 0 8.31 0.327 number of pins n64 cqfp064w 21/22 ST92195B - general information 3.2 ordering information each device is available for production in a user programmable version (otp) as well as in factory coded version (rom). otp devices are shipped to customer with a default blank content ffh, while rom factory coded parts contain the code sent by customer. the common eprom versions for de- bugging and prototyping features the maximum memory size and peripherals of the family. care must be taken to only use resources available on the target device. 3.2.1 transfer of customer code customer code is made up of the rom contents and the list of the selected options (if any). the rom contents are to be sent on diskette, or by electronic means, with the hexadecimal file gener- ated by the development tool. all unused bytes must be set to ffh. figure 11. rom factory coded device types figure 12. otp user programmable device types figure 13. eprom user programmable device types device package temp. range xxx / code name (defined by stmicroelectronics) 1= standard 0 to +70 c b= plastic dip56 t= plastic tqfp64 ST92195B1 ST92195B2 ST92195B3 ST92195B4 ST92195B5 ST92195B6 ST92195B7 device package temp. range code name (defined by stmicroelectronics) 1= 0 to +70 c b= plastic dip56 t= plastic tqfp64 st92t195b7 xxx / device package temp. range 0= 25 c b= ceramic dip 56 pin t= ceramic qfp 64 pin st92e195b7 22/22 ST92195B - general information notes: information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2000 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain sweden - switzerland - united kingdom - u.s.a. http:// www.st.com |
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